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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:35:35 03/03/2012 
-- Design Name: 
-- Module Name:    Processor - Struct
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Processor is
    Port ( clk_i : in  STD_LOGIC;
			  clr_i : in STD_LOGIC;
           instr_ack_i : in  STD_LOGIC;
           instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           data_ack_i : in  STD_LOGIC;
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           int_req : in  STD_LOGIC;
           port_ack_i : in  STD_LOGIC;
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
           data_we_o : out  STD_LOGIC;
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           int_ack : out  STD_LOGIC;
           port_cyc_o : out  STD_LOGIC;
           port_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_word_o : out  STD_LOGIC_VECTOR (7 downto 0)
		);
		
		
		
end Processor;

architecture Struct of Processor is

	component DP is 
   Port (	clk : in  STD_LOGIC;
				clr : in  STD_LOGIC;
				inst_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
				inst_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
				data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
				port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
				data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
				port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
				data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
				port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
				
				--FETCH UNIT
				fu_pc_sel 		: in  STD_LOGIC;
				fu_mux10_sel	: in  STD_LOGIC;
				fu_mux3_sel 	: in  STD_LOGIC_VECTOR (2 downto 0);
				pc_in 			: in	STD_LOGIC_VECTOR (9 downto 0);
				
				--STACK
				st_sel 	: in  STD_LOGIC; -- 0 desapilo (LEO) a 1 apilo (ESCRIBO)
				st_en 	: in  STD_LOGIC; --a 0 no hago nada y a 1 hago algo
				
				--INTERRUPT REG
				interrupt_read : in  STD_LOGIC;
				interrupt_store : in  STD_LOGIC;
				
				--IR
				ir_sel: in STD_LOGIC;
				ir_out_o : out STD_LOGIC_VECTOR (17 downto 0);

				--DATA REGISTER 
				dr_sel : in  STD_LOGIC;
				data_sel : in STD_LOGIC;
				
				--REGISTER FILE
				rf_sel : in  STD_LOGIC;
				w_sel : in STD_LOGIC;
				
				--ALU
				mux8_sel : in  STD_LOGIC;
				alu_op : in  STD_LOGIC_VECTOR (3 downto 0);
				alu_ext : in  STD_LOGIC_VECTOR (2 downto 0);
				ZF : out  STD_LOGIC;
				CF : out  STD_LOGIC;
				
				--ACC
				load_acc_en : in  STD_LOGIC
					
		);
	end component DP;
	
	component ControlUnit is
		Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           ir : in  STD_LOGIC_VECTOR (17 downto 0);
			  instr_ack_in : in STD_LOGIC;
			  data_ack_in : in STD_LOGIC;
			  port_ack_in : in STD_LOGIC;
			  interrupt : in STD_LOGIC;
           data_cyc_o : out STD_LOGIC;
			  port_cyc_o : out STD_LOGIC;
			  instr_cyc_o : out STD_LOGIC;
			  instr_stb_o : out STD_LOGIC;
			  data_stb_o : out STD_LOGIC;
			  port_stb_o : out STD_LOGIC;
			  data_we_o : out STD_LOGIC;
			  port_we_o : out STD_LOGIC;
			  fu_pc_sel : out  STD_LOGIC;
           fu_mux10_sel : out  STD_LOGIC;
           fu_mux3_sel : out  STD_LOGIC_VECTOR (2 downto 0);
           ra_mux9_sel : out  STD_LOGIC;
           ra_mux8_sel : out  STD_LOGIC;
           ra_acc_sel : out  STD_LOGIC;
           ra_mux15_sel : out  STD_LOGIC;
           ra_data16_sel : out  STD_LOGIC;
			  interrupt_read : out STD_LOGIC;
			  int_ack : out STD_LOGIC;
			  interrupt_store : out STD_LOGIC;
			  interrupt_enable : out STD_LOGIC;
           ra_reg_sel : out  STD_LOGIC;
           ra_ext : out  STD_LOGIC_VECTOR (2 downto 0);
			  ra_opcode : out STD_LOGIC_VECTOR (3 downto 0);
           st_sel : out  STD_LOGIC;
           st_en : out  STD_LOGIC;
           ir_sel : out  STD_LOGIC;
			  ra_zf : in STD_LOGIC;
			  ra_cf : in STD_LOGIC
			  );
	end component ControlUnit;
	
	signal pc : STD_LOGIC_VECTOR (9 downto 0);
	signal fu_pc_sel :  STD_LOGIC;
	signal fu_mux10_sel :  STD_LOGIC;
	signal fu_mux3_sel :  STD_LOGIC_VECTOR (2 downto 0);
	signal ra_mux9_sel :  STD_LOGIC;
	signal ra_mux8_sel :  STD_LOGIC;
	signal ra_acc_sel :  STD_LOGIC;
	signal ra_mux15_sel :  STD_LOGIC;
	signal ra_data16_sel :  STD_LOGIC;
	signal interrupt_read : STD_LOGIC;
	signal interrupt_store : STD_LOGIC;
	signal interrupt_enable : STD_LOGIC;
	signal ra_reg_sel :  STD_LOGIC;
	signal ra_ext :  STD_LOGIC_VECTOR (2 downto 0);
	signal ra_opcode : STD_LOGIC_VECTOR (3 downto 0);
	signal st_sel :  STD_LOGIC;
	signal st_en :  STD_LOGIC;
	signal ir_sel :  STD_LOGIC;
	signal ir_out_p : STD_LOGIC_VECTOR (17 downto 0);
	signal ra_zf : STD_LOGIC;
	signal ra_cf : STD_LOGIC;
	
begin
	dataPath:DP port map(
		clk =>  clk_i,
		clr =>  clr_i,
		inst_addr_o => instr_addr_o ,
		inst_word_i => instr_word_i ,
		data_word_i => data_word_i,
		port_word_i => port_word_i ,
		data_word_o => data_word_o,
		port_word_o => port_word_o,
		data_addr_o => data_addr_o,
		port_addr_o => port_addr_o,
		fu_pc_sel => fu_pc_sel ,
		fu_mux10_sel => fu_mux10_sel,
		fu_mux3_sel => fu_mux3_sel,
		pc_in => pc,
		st_sel => st_sel ,
		st_en => st_en ,
		ZF =>  ra_zf,
		CF =>  ra_cf,
		interrupt_read =>  interrupt_read,
		interrupt_store =>  interrupt_store,
		dr_sel => ra_mux15_sel ,
		rf_sel => ra_reg_sel ,
		w_sel =>ra_mux9_sel ,
		mux8_sel =>ra_mux8_sel  ,
		alu_op =>ra_opcode ,
		alu_ext => ra_ext ,
		load_acc_en => ra_acc_sel,
		ir_sel => ir_sel,
		ir_out_o => ir_out_p,
		data_sel =>ra_data16_sel
	);
	
	cu:ControlUnit port map(
		clk =>  clk_i,
		clr => clr_i,
		--ir => instr_word_i ,
		ir => ir_out_p,
		instr_ack_in=> instr_ack_i,
		data_ack_in=> data_ack_i,
		port_ack_in=> port_ack_i,
		interrupt => int_req,
		data_cyc_o => data_cyc_o,
		port_cyc_o => port_cyc_o,
			  instr_cyc_o => instr_cyc_o,--NUEVO
			  instr_stb_o => instr_stb_o,--NUEVO
		data_stb_o => data_stb_o,
		port_stb_o => port_stb_o,
		data_we_o => data_we_o,
		port_we_o => port_we_o,
		fu_pc_sel =>  fu_pc_sel,
		fu_mux10_sel =>  fu_mux10_sel,
		fu_mux3_sel =>  fu_mux3_sel,
		ra_mux9_sel =>  ra_mux9_sel,
		ra_mux8_sel =>  ra_mux8_sel,
		ra_acc_sel =>  ra_acc_sel,
		ra_mux15_sel =>  ra_mux15_sel,
		ra_data16_sel =>  ra_data16_sel,
		interrupt_read => interrupt_read,
		int_ack => int_ack,
		interrupt_store => interrupt_store,
		interrupt_enable =>  interrupt_enable,
		ra_reg_sel =>  ra_reg_sel,
		ra_ext =>  ra_ext,
		ra_opcode => ra_opcode,
		st_sel => st_sel,
		st_en =>  st_en,
		ir_sel =>  ir_sel,
		ra_zf => ra_zf,
		ra_cf => ra_cf
	);
					
  
  
end Struct;

